Module ariths_gen.multi_bit_circuits.others.bit_reduce
Classes
class AndReduce (a: Bus,
prefix: str = '',
name: str = 'andreduce',
**kwargs)-
Expand source code
class AndReduce(BitReduce): def __init__(self, a: Bus, prefix: str = "", name: str = "andreduce", **kwargs): super().__init__(a=a, gate=AndGate, prefix=prefix, name=name, **kwargs)Class representing tree reducer circuit. Doent work for NAND gate!
Ancestors
Inherited members
BitReduce:add_componentget_blif_code_flatget_blif_code_hierget_c_code_flatget_c_code_hierget_cgp_code_flatget_circuit_blifget_circuit_cget_circuit_defget_circuit_gatesget_circuit_vget_circuit_wire_indexget_circuit_wiresget_component_typesget_declaration_blifget_declaration_c_flatget_declaration_c_hierget_declaration_v_flatget_declaration_v_hierget_declarations_c_hierget_declarations_v_hierget_function_blif_flatget_function_block_blifget_function_block_cget_function_block_vget_function_blocks_blifget_function_blocks_cget_function_blocks_vget_function_out_blifget_function_out_c_flatget_function_out_c_hierget_function_out_python_flatget_function_out_v_flatget_function_out_v_hierget_hier_subcomponent_defget_includes_cget_init_c_flatget_init_c_hierget_init_python_flatget_init_v_flatget_init_v_hierget_instance_numget_invocation_blif_hierget_invocations_blif_hierget_multi_bit_componentsget_one_bit_componentsget_out_invocation_cget_out_invocation_vget_outputs_cgpget_parameters_cgpget_previous_componentget_prototype_blifget_prototype_cget_prototype_pythonget_prototype_vget_python_code_flatget_triplets_cgpget_unique_typesget_v_code_flatget_v_code_hiersave_wire_id
class BitReduce (a: Bus,
gate: TwoInputLogicGate,
prefix: str = '',
name: str = 'bitreduce',
**kwargs)-
Expand source code
class BitReduce(GeneralCircuit): """Class representing tree reducer circuit. Doent work for NAND gate! """ def __init__(self, a: Bus, gate: TwoInputLogicGate, prefix: str = "", name: str = "bitreduce", **kwargs): self.N = a.N super().__init__(name=name, prefix=prefix, inputs=[a], out_N=1, **kwargs) # tree reduction def create_tree(a: Bus, depth: int, branch="A"): #print(a) if a.N == 1: return a[0] else: half = a.N // 2 b_in = Bus(N=half, prefix=f"b_inn{depth}A") c_in = Bus(N=a.N - half, prefix=f"b_inn{depth}B") #print(a, half, a.N) for i, j in enumerate(range(half)): b_in[i] = a[j] for i, j in enumerate(range(half, a.N)): c_in[i] = a[j] b = create_tree(b_in, depth=depth + 1, branch = branch + "A") c = create_tree(c_in, depth= depth + 1, branch = branch + "B") d = gate(a=b, b=c, prefix = f"{self.prefix}_red_{branch}_{depth}") self.add_component(d) return d.out sumwire = create_tree(self.a, 0, "X") #print(sumbus) self.out[0] = sumwireClass representing tree reducer circuit. Doent work for NAND gate!
Ancestors
Subclasses
Inherited members
GeneralCircuit:add_componentget_blif_code_flatget_blif_code_hierget_c_code_flatget_c_code_hierget_cgp_code_flatget_circuit_blifget_circuit_cget_circuit_defget_circuit_gatesget_circuit_vget_circuit_wire_indexget_circuit_wiresget_component_typesget_declaration_blifget_declaration_c_flatget_declaration_c_hierget_declaration_v_flatget_declaration_v_hierget_declarations_c_hierget_declarations_v_hierget_function_blif_flatget_function_block_blifget_function_block_cget_function_block_vget_function_blocks_blifget_function_blocks_cget_function_blocks_vget_function_out_blifget_function_out_c_flatget_function_out_c_hierget_function_out_python_flatget_function_out_v_flatget_function_out_v_hierget_hier_subcomponent_defget_includes_cget_init_c_flatget_init_c_hierget_init_python_flatget_init_v_flatget_init_v_hierget_instance_numget_invocation_blif_hierget_invocations_blif_hierget_multi_bit_componentsget_one_bit_componentsget_out_invocation_cget_out_invocation_vget_outputs_cgpget_parameters_cgpget_previous_componentget_prototype_blifget_prototype_cget_prototype_pythonget_prototype_vget_python_code_flatget_triplets_cgpget_unique_typesget_v_code_flatget_v_code_hiersave_wire_id
class OrReduce (a: Bus,
prefix: str = '',
name: str = 'orreduce',
**kwargs)-
Expand source code
class OrReduce(BitReduce): def __init__(self, a: Bus, prefix: str = "", name: str = "orreduce", **kwargs): super().__init__(a=a, gate=OrGate, prefix=prefix, name=name, **kwargs)Class representing tree reducer circuit. Doent work for NAND gate!
Ancestors
Inherited members
BitReduce:add_componentget_blif_code_flatget_blif_code_hierget_c_code_flatget_c_code_hierget_cgp_code_flatget_circuit_blifget_circuit_cget_circuit_defget_circuit_gatesget_circuit_vget_circuit_wire_indexget_circuit_wiresget_component_typesget_declaration_blifget_declaration_c_flatget_declaration_c_hierget_declaration_v_flatget_declaration_v_hierget_declarations_c_hierget_declarations_v_hierget_function_blif_flatget_function_block_blifget_function_block_cget_function_block_vget_function_blocks_blifget_function_blocks_cget_function_blocks_vget_function_out_blifget_function_out_c_flatget_function_out_c_hierget_function_out_python_flatget_function_out_v_flatget_function_out_v_hierget_hier_subcomponent_defget_includes_cget_init_c_flatget_init_c_hierget_init_python_flatget_init_v_flatget_init_v_hierget_instance_numget_invocation_blif_hierget_invocations_blif_hierget_multi_bit_componentsget_one_bit_componentsget_out_invocation_cget_out_invocation_vget_outputs_cgpget_parameters_cgpget_previous_componentget_prototype_blifget_prototype_cget_prototype_pythonget_prototype_vget_python_code_flatget_triplets_cgpget_unique_typesget_v_code_flatget_v_code_hiersave_wire_id