Module `ariths_gen.multi_bit_circuits.adders.ripple_carry_adder`

Classes

class SignedRippleCarryAdder (a: Bus, b: Bus, prefix: str = '', name: str = 's_rca', **kwargs)

Expand source code

class SignedRippleCarryAdder(UnsignedRippleCarryAdder, GeneralCircuit):
    """Class representing signed ripple carry adder.

    Signed ripple carry adder represents N-bit signed adder which is composed of
    N one bit adders, where the first is a half adder and rest are full adders.
    At last XOR gates are used to ensure proper sign extension.

    Its downside is its long propagation delay the bigger the circuit is.

    ```
      B3 A3      B3 A3      B2 A2      B1 A1      B0 A0
      │  │       │  │       │  │       │  │       │  │
    ┌─▼──▼─┐   ┌─▼──▼─┐   ┌─▼──▼─┐   ┌─▼──▼─┐   ┌─▼──▼─┐
    │ SIGN │ C4│      │ C3│      │ C2│      │ C1│      │
    │Extend│◄──┤  FA  │◄──┤  FA  │◄──┤  FA  │◄──┤  HA  │
    │      │   │      │   │      │   │      │   │      │
    └──┬───┘   └──┬───┘   └──┬───┘   └──┬───┘   └──┬───┘
       ▼          ▼          ▼          ▼          ▼
      Cout        S3         S2         S1         S0
    ```

    Description of the __init__ method.

    Args:
        a (Bus): First input bus.
        b (Bus): Second input bus.
        prefix (str, optional): Prefix name of signed rca. Defaults to "".
        name (str, optional): Name of signed rca. Defaults to "s_rca".
    """
    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_rca", **kwargs):
        # Signed bus length extension
        N = max(a.N, b.N)
        a.bus_extend(N=N, prefix=a.prefix, desired_extension_wire=a.get_wire(a.N-1))
        b.bus_extend(N=N, prefix=b.prefix, desired_extension_wire=b.get_wire(b.N-1))
        super().__init__(a=a, b=b, prefix=prefix, name=name, signed=True, **kwargs)

        # Additional XOR gates to ensure correct sign extension in case of sign addition
        sign_xor_1 = XorGate(self.get_previous_component(1).a, self.get_previous_component(1).b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
        self.add_component(sign_xor_1)
        sign_xor_2 = XorGate(sign_xor_1.out, self.get_previous_component(2).get_carry_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
        self.add_component(sign_xor_2)
        self.out.connect(self.N, sign_xor_2.out)

Class representing signed ripple carry adder.

Signed ripple carry adder represents N-bit signed adder which is composed of N one bit adders, where the first is a half adder and rest are full adders. At last XOR gates are used to ensure proper sign extension.

Its downside is its long propagation delay the bigger the circuit is.

  B3 A3      B3 A3      B2 A2      B1 A1      B0 A0
  │  │       │  │       │  │       │  │       │  │
┌─▼──▼─┐   ┌─▼──▼─┐   ┌─▼──▼─┐   ┌─▼──▼─┐   ┌─▼──▼─┐
│ SIGN │ C4│      │ C3│      │ C2│      │ C1│      │
│Extend│◄──┤  FA  │◄──┤  FA  │◄──┤  FA  │◄──┤  HA  │
│      │   │      │   │      │   │      │   │      │
└──┬───┘   └──┬───┘   └──┬───┘   └──┬───┘   └──┬───┘
   ▼          ▼          ▼          ▼          ▼
  Cout        S3         S2         S1         S0

Description of the init method.

Args

a : Bus: First input bus.
b : Bus: Second input bus.
prefix : str, optional: Prefix name of signed rca. Defaults to "".
name : str, optional: Name of signed rca. Defaults to "s_rca".

Ancestors

UnsignedRippleCarryAdder
GeneralCircuit

Inherited members

UnsignedRippleCarryAdder:
- add_component
- get_blif_code_flat
- get_blif_code_hier
- get_c_code_flat
- get_c_code_hier
- get_cgp_code_flat
- get_circuit_blif
- get_circuit_c
- get_circuit_def
- get_circuit_gates
- get_circuit_v
- get_circuit_wire_index
- get_circuit_wires
- get_component_types
- get_declaration_blif
- get_declaration_c_flat
- get_declaration_c_hier
- get_declaration_v_flat
- get_declaration_v_hier
- get_declarations_c_hier
- get_declarations_v_hier
- get_function_blif_flat
- get_function_block_blif
- get_function_block_c
- get_function_block_v
- get_function_blocks_blif
- get_function_blocks_c
- get_function_blocks_v
- get_function_out_blif
- get_function_out_c_flat
- get_function_out_c_hier
- get_function_out_python_flat
- get_function_out_v_flat
- get_function_out_v_hier
- get_hier_subcomponent_def
- get_includes_c
- get_init_c_flat
- get_init_c_hier
- get_init_python_flat
- get_init_v_flat
- get_init_v_hier
- get_instance_num
- get_invocation_blif_hier
- get_invocations_blif_hier
- get_multi_bit_components
- get_one_bit_components
- get_out_invocation_c
- get_out_invocation_v
- get_outputs_cgp
- get_parameters_cgp
- get_previous_component
- get_prototype_blif
- get_prototype_c
- get_prototype_python
- get_prototype_v
- get_python_code_flat
- get_triplets_cgp
- get_unique_types
- get_v_code_flat
- get_v_code_hier
- save_wire_id

class UnsignedRippleCarryAdder (a: Bus, b: Bus, prefix: str = '', name: str = 'u_rca', **kwargs)

Expand source code

class UnsignedRippleCarryAdder(GeneralCircuit):
    """Class representing unsigned ripple carry adder.

    Unsigned ripple carry adder represents N-bit unsigned adder which is composed of
    N one bit adders, where the first is a half adder and rest are full adders.

    Its downside is its long propagation delay the bigger the circuit is.

    ```
          B3 A3      B2 A2      B1 A1      B0 A0
          │  │       │  │       │  │       │  │
        ┌─▼──▼─┐   ┌─▼──▼─┐   ┌─▼──▼─┐   ┌─▼──▼─┐
        │      │ C3│      │ C2│      │ C1│      │
     ┌──┤  FA  │◄──┤  FA  │◄──┤  FA  │◄──┤  HA  │
     │  │      │   │      │   │      │   │      │
     │  └──┬───┘   └──┬───┘   └──┬───┘   └──┬───┘
     ▼     ▼          ▼          ▼          ▼
    Cout   S3         S2         S1         S0
    ```

    Description of the __init__ method.

    Args:
        a (Bus): First input bus.
        b (Bus): Second input bus.
        prefix (str, optional): Prefix name of unsigned rca. Defaults to "".
        name (str, optional): Name of unsigned rca. Defaults to "u_rca".
    """
    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_rca", **kwargs):
        self.N = max(a.N, b.N)
        super().__init__(inputs=[a, b], prefix=prefix, name=name, out_N=self.N+1, **kwargs)

        # Bus sign extension in case buses have different lengths
        self.a.bus_extend(N=self.N, prefix=a.prefix)
        self.b.bus_extend(N=self.N, prefix=b.prefix)

        # Gradual addition of 1-bit adder components
        for input_index in range(self.N):
            # First adder is a half adder
            if input_index == 0:
                obj_adder = HalfAdder(self.a.get_wire(input_index), self.b.get_wire(input_index), prefix=self.prefix+"_ha")
            # Rest adders are full adders
            else:
                obj_adder = FullAdder(self.a.get_wire(input_index), self.b.get_wire(input_index), self.get_previous_component().get_carry_wire(), prefix=self.prefix+"_fa"+str(input_index))

            self.add_component(obj_adder)
            self.out.connect(input_index, obj_adder.get_sum_wire())
            if input_index == (self.N-1):
                self.out.connect(self.N, obj_adder.get_carry_wire())

Class representing unsigned ripple carry adder.

Unsigned ripple carry adder represents N-bit unsigned adder which is composed of N one bit adders, where the first is a half adder and rest are full adders.

Its downside is its long propagation delay the bigger the circuit is.

      B3 A3      B2 A2      B1 A1      B0 A0
      │  │       │  │       │  │       │  │
    ┌─▼──▼─┐   ┌─▼──▼─┐   ┌─▼──▼─┐   ┌─▼──▼─┐
    │      │ C3│      │ C2│      │ C1│      │
 ┌──┤  FA  │◄──┤  FA  │◄──┤  FA  │◄──┤  HA  │
 │  │      │   │      │   │      │   │      │
 │  └──┬───┘   └──┬───┘   └──┬───┘   └──┬───┘
 ▼     ▼          ▼          ▼          ▼
Cout   S3         S2         S1         S0

Description of the init method.

Args

a : Bus: First input bus.
b : Bus: Second input bus.
prefix : str, optional: Prefix name of unsigned rca. Defaults to "".
name : str, optional: Name of unsigned rca. Defaults to "u_rca".

Classes

Args

Ancestors

Inherited members

Args

Ancestors

Subclasses

Inherited members